Programmable integrated semiconductor circuits comprise logic cells, which may be configurable and are wired among one another in a suitable manner. The logic cells are formed in an active layer of the semiconductor circuit, said active layer containing the CMOS transistor structures (i.e. doped semiconductor regions and gate layers) of the logic cell. The logic functions of the logic cells are defined by one or a plurality of wiring layers that are situated above the active layer and realize the internal wiring of the logic cell. Such wiring layers that define the logic function of a cell are also referred to as “intraconnect”. Configurable logic cells are known in the literature e.g. as CLB (configurable logic block). The designation logic function block is used hereinafter for a logic cell.
Every logic function block has to be fed a supply voltage and, in the case of a more complex construction, also has to be fed, if appropriate, global signals such as RESET, scan test and clock supply. Further wiring layers are provided for this in the semiconductor circuit. Moreover, wiring layers that perform the routing for the input and output signals of the logic function blocks are required. These are referred to as “interconnect”.
Whereas the wiring layers for the power supply, the clock supply, and in some cases also the wiring layer(s) for the definition of the function of the logic function blocks are fixedly predetermined, the signal routing is always customizable. For the application-specific adaptability or customizability of the signal routing, it is possible to provide mask-programmable wiring layers for the signal routing and/or mask-programmable insulation layers between the wiring layers or electrically controllable switches for the flexible configuration of the “interconnect”.
Programmable semiconductor circuits differ inter alia by virtue of the complexity of the logic function blocks used and the degree of customization of the wirings. Gate arrays use individual transistors or very small groups of transistors as logic function blocks, while the entire wiring (interconnect and intraconnect) is customized. The advantage of gate arrays consists in their high logic density, but the high individuality of the metallization masks causes high costs for the fabrication of the individual wiring layers. In modem fabrication technologies, the costs for the masks of the active structures form the principal proportion of costs for the set of masks. In gate arrays, the mask costs for the active structures can be distributed between a plurality of applications by means of predefinition. However, all wiring planes including the wiring in the intervening insulation layers (vias) always have to be created anew since the possibilities for utilizing predefined wiring planes have not been available heretofore.
In PLDs (Programmable Logic Devices), simple, prefabricated gates, instead of transistors, are used as logic function blocks. One example of the construction of a PLD, in which the signal routing is realized by two wiring layers with lines that run orthogonally and with an intervening insulation layer in which feedthroughs (vias) are formed between the lines of the metallization layers, is described in the document U.S. Pat. No. 4,197,555.
So-called sASICs (structured Application Specific Integrated Circuits) use partially or completely prefabricated logic function blocks having relatively high complexity. Typical logic function blocks contain combinatorial components (for example complex gates, multiplexers and a plurality of inverters or smaller look-up tables) and sequential components (for example flip-flop, multivibrators). The logic function blocks can be combined with distributed memories structures. A logic function block can perform a plurality of logic functions, in which case the selection can either be realized in the production sequence by means of a mask-programmable internal wiring “intraconnect” or can be made during operation by means of external signals or signals stored on-chip, which are fed e.g. to multiplexers within the fixed logic function block.
For the customizability of a semiconductor circuit, it is possible, in principle, for both the wiring layers for the internal wiring of the individual logic function blocks and the wiring layers for the signal routing between the logic function blocks to be varied in customizable fashion. It generally holds true that, for a cost-effective wiring, on the one hand, as many predefined, i.e. “fixed”, wiring layers as possible are to be used and, on the other hand, the total number of wiring layers required is to remain as low as possible.
Typically, in the case of sASICs, mask-programmable wiring layers are placed into the upper metal layers in order to ensure that a customization of the integrated circuit has to be performed only in the upper metal layers. As a result, sASICs for different applications can be produced with the same set of masks, apart from the upper layers that can be programmed in customized fashion. This affords cost advantages in production since the integrated semiconductor circuit can initially be fabricated in non-customized fashion over many process steps in correspondingly high numbers and the customization has to be effected only in the final process steps. What is disadvantageous, however, is that long, vertical multiple feedthroughs (so-called stacked vias) between the customized upper wiring layers and the active layer of the logic function blocks impede the line routing in intervening wiring layers. A further disadvantage is that experience shows that fabricating such multiple feedthroughs extending over a plurality of layer strata poses difficulties and can therefore impair the production yield.
Programmable semiconductor circuits can furthermore be differentiated by the regularity of the arrangement of the function blocks. Whereas function blocks in gate arrays are arranged in a regular cell zone in matrix form (which is referred to as an array), function blocks in traditional ASICs can be distributed in an irregularly positioned manner over the semiconductor circuit. ASICs whose logic function blocks are likewise arranged in a regular array are also referred to as structured ASICs.
sASICs are differentiated by the fact that they are constructed either with or without interspaces (so-called channels) between the individual logic function blocks. In sASICs which use the channel technique, a large part of the signal routing or the entire signal routing between the logic function blocks is carried out within the channels. In channel-free sASICs, the logic function blocks adjoin one another essentially without any gaps, the signal routing, as already described, being carried out in one or a plurality of wiring layers above the active layer containing the functional elements.
The document U.S. Pat. No. 6,613,611 B1 describes a structured ASIC whose function blocks may contain combinatorial and sequential functions and also memory functions and are arranged next to one another without any gaps in the manner of an array. The signal routing is realized by at least two metallization layers lying one above the other with mutually orthogonal conductor segments. The deeper one of the two metallization layers (e.g. M3) is fixedly predetermined, whereas the overlying metallization layer (M4) is customizable. Customizable metallization layers are always realized as topmost metallization layers.
A further aspect in the design of semiconductor circuits comprising a plurality of function blocks consists in the need to provide long lines at the output of a function block, given a large load or large fan-out of the signal paths, with a driver that compensates for the long delay of a datum that otherwise arises. Furthermore, signals that are transmitted over long wiring lines have to be refreshed. It is thus necessary to provide distributed driver resources within the semiconductor circuit in such a way that, if possible, all propagation time problems can be solved within the semiconductor circuit, which may also comprise the targeted delay of a signal path. On the other hand, however, the semiconductor circuit should not be enlarged unnecessarily by many, ultimately unutilized drivers.
The following approaches are known for solving this problem:
1. The problem is solved in a function-block-based manner in that each output of a logic function block is assigned a driver having a high strength, or the output can be switched over between a plurality of drivers having differing strengths that are kept available. In the case of this approach, some logic function blocks do not utilize or do not fully utilize their drivers, and at the same time situations usually occur in which the existing driver strength does not suffice for some critical paths in the semiconductor circuit.
2. As an alternative, a common driver cell may be assigned to a certain number of logic function blocks in the wiring structure of the semiconductor circuit. The problem of unused or insufficient driver resources can be solved better in this way. Such a local common driver cell must be able to be reached from all associated logic function blocks in the vicinity, which is associated with a higher wiring outlay. Local peaks in driver demand (hotspots) also cannot be completely satisfied in this way.
3. Modem FPGA (Field Programmable Gate Array) architectures combine local drivers in accordance with (1) with drivers in the local wiring region in accordance with (2) and further global driver resources. In this way, generally, even critical signals can be driven sufficiently. However, this concept is very complex and requires a great deal of chip area.